Many integrated circuits (ICs) operate with a supply voltage source whose output is at a nominal level (i.e., +VDD) which can be allowed to vary only within preselected limits (i.e., a voltage range) before the ICs fail to operate properly. Power-out reset circuits are used to monitor the level of +VDD and to provide a signal when the level of +VDD exceeds the preselected voltage range on the high side or the low side of the voltage range. Typically +VDD is used to power both the ICs and the power-out reset circuits.
One such typical power-out reset circuit uses voltage generators to generate reference voltages, i.e., Vbg (the silicon bandgap voltage) and VIbg (a reference voltage related to the band gap current) which serve as inputs to over voltage and under voltage detectors which each have a comparator circuit which compares Vbg to an attenuated +VDD. Vbg is typically essentially constant in voltage over a useful temperature range. VIbg is typically coupled to a control terminal of a current source of each of the voltage detectors. VIbg is characterized such that the current it causes to be generated by the current source is essentially constant over a useful temperature range. Each detector compares the voltage level of Vbg with that of an attenuated level of the actual level of +VDD. If the level of +VDD is higher than a preselected high level (+Vhigh), the over voltage detector provides an output signal indicative of this condition. If the level of +VDD is lower than a preselected low level (+Vlow), the under voltage detector provides an output signal indicative of this condition. Output logic circuitry coupled to outputs of the over and under voltage detectors provides an output signal which is indicative of whether the voltage level of +VDD is within the preselected voltage level limits (+Vhigh to +Vlow) or outside of same.
There are commonly encountered problems such as false triggering at power-up due to the comparators becoming active before the reference voltage (Vbg) has stabilized, false triggering during normal operation due to noise glitches, and a false indication of normal operation at low +VDD after the reference voltages have become invalid.
It is desirable to have a power-on reset circuit which reduces the above described problems.